Contributed by Claus Buchholz

In 1977 the TI-57 replaced the SR-56 and retailers dropped prices on the wonderful 56, enabling this poor high-school senior to buy his first programmable calculator.

The 57 used more modern, less expensive, single-chip technology, but TI struggled to approach the capabilities of the 56 with only half the RAM. They compromised by sharing user memory registers with internal operands. To offset the smaller program space, they even borrowed ideas such as merged program codes from their arch-rival.

TI published many details of the internal architecture, including ROM object code, in US Patent 4125901 and others. The 57 (as well as its siblings, TI-55, TI-51-III, TI-42, and MBA) contains 4 operating registers plus 16 storage registers, each with 16 4-bit digits (a mere 160 bytes). A few years ago, a clever fellow called HrastProgrammer used the patent disclosures to create an emulator for the 57's CPU and ROM. Using his program, I have deduced how the 57 stores numbers and programs in its limited RAM. The table below shows the chosen organization and explains some of the 57's usage restrictions.

TI-57 Storage Register Allocation
by Claus Buchholz using TI-57E by HrastProgrammer

Reg	D15	D14	D13	D12	...	D2	D1	D0
X0	(0	O0	A0 N	A0 MH	...	A0 ML	A0 EH	A0 EL
X1	(1	O1	A1 N	A1 MH	...	A1 ML	A1 EH	A1 EL
X2	(2	O2	R6 N	R6 MH	...	R6 ML	R6 EH	R6 EL
X3	(3	O3	R5 N	R5 MH	...	R5 ML	R5 EH	R5 EL
X4	SC	?	R7 N	R7 MH	...	R7 ML	R7 EH	R7 EL
X5	PC H	PC L	R0 N	R0 MH	...	R0 ML	R0 EH	R0 EL
X6	S1 H	S1 L	R1 N	R1 MH	...	R1 ML	R1 EH	R1 EL
X7	S2 H	S2 L	R2 N	R2 MH	...	R2 ML	R2 EH	R2 EL
Y0	P00 H	P00 L	P01 H	P01 L	...	P06 L	P07 H	P07 L
Y1	P08 H	P08 L	P09 H	P09 L	...	P14 L	P15 H	P15 L
Y2	P16 H	P16 L	P17 H	P17 L	...	P22 L	P23 H	P23 L
Y3	P24 H	P24 L	P25 H	P25 L	...	P30 L	P31 H	P31 L
Y4	P32 H	P32 L	P33 H	P33 L	...	P38 L	P39 H	P39 L
Y5	P40 H	P40 L	P41 H	P41 L	...	P46 L	P47 H	P47 L
Y6	P48 H	P48 L	R3 N	R3 MH	...	R3 ML	R3 EH	R3 EL
Y7	P49 H	P49 L	R4 N	R4 MH	...	R4 ML	R4 EH	R4 EL

D - Digit 0-15 (4 bits, BCD or binary)
X - Internal X Register 0-7
Y - Internal Y Register 0-7
R - User Memory Register 0-7
A - AOS Pending Operand 0-3 (A2=R6, A3=R5)
O - AOS Pending Operation 0-3 (2=+, 4=*, 8=y^x)
( - Open Parenthesis Counter 0-3
PC - Program Counter
P - User Program Step 00-49
SC - Subroutine Counter
S - Subroutine Return Address 1-2
N - Sign Flags (1=Negative Mantissa, 2=Negative Exponent, 4=Inverse Operation)
M - Mantissa
E - Exponent
H - Most Significant Digit
L - Least Significant Digit

Claus Buchholz
Michigan, USA